By Bamberg P., Sternberg S.
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Extra resources for A Course in Mathematics for Students of Physics, vol. 1
Reading or writing ORA does not clear the CA2 interrupt flag. Clear IFRO by writing logic I into IFRO. I 0 0 CA2 Handshake Output Mode-Set CA2 output low on a read or write of the Peripheral A Output Register. Reset CA2 high with an active transition on CAI. I 0 I CA2 Pulse Output Mode-CA2 goes low for one cycle following a read or write of the Peripheral A Output Register. I I 0 CA2 Output Low Mode-The CA2 output is held low in this mode. I I I CA2 Output High Mode-The CA2 output is held high in this mode.
The registers are 41 6502 APPLICATIONS BOOK shown on Fig 2-28. They share the same memory address. One is an input register, the other an output register. The interrupt flag register IFR is an input register. Each bit position from O to will be set whenever an interrupt is detected on any of the external lines (CAI, CA2, CBI, CB2), on the shift register (SR), on any of the two timers (Tl and T2). Bit 7 is set whenever any other bit is set in the register. The interrupt enable register (IER) will enable or disable interrupts from any of the sources.
Assuming that we simply have to send one word of 8 bits out, no waiting loop is necessary here to determine whether the shift is finished or not. The program appears below: SHIFTOUT LDA STA LDA STA LDA #0 ACR #$18 ACR $20 STA SR CLEAR SR cl>2 OUT MODE READ DAT A FROM MEMORY As above, the shift register is first cleared, then the ACR is loaded with the value "18" hexadecimal, which specifies the combination "110" into bit positions 4,3 and 2. This specifies the shift out at a rate controlled by phase 2 of the system clock: LDA STA 58 #0 ACR THE INPUT OUTPUT CHIPS LDA STA #$18 ACR The data is then fetched from memory location 20, and deposited into the shift register.
A Course in Mathematics for Students of Physics, vol. 1 by Bamberg P., Sternberg S.